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Provisional Data Sheet No. PD - 9.1666A
IRFE130 REPETITIVE AVALANCHE AND dv/dt RATED JANTX2N6796U (R) HEXFET TRANSISTOR JANTXV2N6796U [REF:MIL-PRF-19500/557]
N-CHANNEL 100Volt, 0.18, HEXFET
The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. The LCC provides designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference. HEXFET transistors also feature all of the well-established advantages of MOSFETs, such as voltage control, very fast switching, ease of paralleling and electrical parameter temperature stability. They are well-suited for applications such as switching power supplies, motor controls, inverters, choppers, audio amplifiers and high-energy pulse circuits, and virtually any application where high reliability is required.
Product Summary
Part Number IRFE130 BVDSS 100V RDS(on) 0.18 ID 8.0A
Features:
n n n n n n
Hermetically Sealed Simple Drive Requirements Ease of Paralleling Small footprint Surface Mount Lightweight
Absolute Maximum Ratings
Parameter
ID @ VGS = 10V, TC = 25C ID @ VGS = 10V, TC = 100C IDM PD @ TC = 25C VGS EAS dv/dt TJ TSTG Continuous Drain Current Continuous Drain Current Pulsed Drain Current Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Peak Diode Recovery dv/dt Operating Junction Storage Temperature Range Surface Temperature Weight IRFE130, JANTX-, JANTXV-, 2N6796U Units 8.0 A 5.0 32 25 W 0.17 W/K 20 V 134 mJ 8.3 V/ns -55 to 150
o
C
300 ( for 5 seconds) 0.42 (typical)
g 11/13/97
IRFE130, JANTX-, JANTXV-, 2N6796U Device
Electrical Characteristics @ Tj = 25C (Unless Otherwise Specified)
Parameter
BVDSS Drain-to-Source Breakdown Voltage BVDSS/TJ Temperature Coefficient of Breakdown Voltage RDS(on) Static Drain-to-Source On-State Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance IDSS Zero Gate Voltage Drain Current
Min
100 -- -- -- 2.0 3.0 -- -- -- -- -- -- -- -- -- -- -- -- --
Typ Max Units
-- 0.11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.8 4.3 -- -- 0.18 0.207 4.0 -- 25 250 100 -100 29 6.5 17 30 75 40 45 -- -- V V/C V S( ) A
Test Conditions
VGS =0 V, ID = 1.0mA Reference to 25C, ID = 1.0mA VGS = 10V, ID = 5.0A VGS = 10V, ID = 8.0A VDS = VGS, ID = 250A VDS > 15V, IDS = 5.0A VDS= 0.8 x Max Rating,VGS=0V VDS = 0.8 x Max Rating VGS = 0V, TJ = 125C VGS = 20 V VGS = -20V VGS = 10V, ID = 8.0A VDS = Max Rating x 0.5 VDD = 50V, ID = 8.0A, RG = 7.5
IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance
nA nC
ns
M a u e f o d i pdt e s r d r m ra n a o de. i
ybl hw Modified MOSFET s m o s o ig te itra idcacs n h nenl nutne.
nH
Maue fo cne o esrd rm etr f suc pdt teedo ore a o h n f suc bnigwr o r e o d n i e.
Ciss Coss Crss
Input Capacitance Output Capacitance Reverse Transfer Capacitance
-- -- --
660 260 51
-- -- --
pF
VGS = 0V, VDS = 25 V f = 1.0MHz
Source-Drain Diode Ratings and Characteristics
Parameter
IS ISM VSD trr QRR ton Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min Typ Max Units
-- -- -- -- -- -- -- -- -- -- 8.0 32 1.5 300 970
Test Conditions
Modified MOSFET symbol showing the integral reverse p-n junction rectifier. Tj = 25C, IS = 8.0A, VGS = 0V Tj = 25C, IF = 8.0A, di/dt 100A/s VDD 50V
A
V ns nC
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
RthJC RthJPCB Junction-to-Case Junction-to-PC Board
Min Typ Max
-- -- -- -- 5.0
Units
K/W
Test Conditions
19
Soldered to a copper clad PC board
Details of notes
through are on the last page
IRFE130, JANTX-, JANTXV-, 2N6796U Device
100
100
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
10
4.5V
4.5V
1
1
0.1 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 0.1
20s PULSE WIDTH TJ = 150 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance (Normalized)
100
2.5
I = 7.4A IDD = 8.0 A
I D , Drain-to-Source Current (A)
TJ = 25 C TJ = 150 C
2.0
10
1.5
1.0
1
0.5
0.1 4 5 6 7
V DS = 50V 20s PULSE WIDTH 8 9 10
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature C) (
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRFE130, JANTX-, JANTXV-, 2N6796U Device
1200
1000
VGS , Gate-to-Source Voltage (V)
VGS = Ciss = Crss = Coss =
0V, f = 1MHz Cgs + Cgd , Cds SHORTED Cgd Cds + Cgd
20
ID = 8.0 A 7.4
16
V DS= 80V V DS= 50V V DS= 20V
C, Capacitance (pF)
800
Ciss
12
600
Coss
400
8
200
4
Crss
0 1 10 100
0 0 6 12
FOR TEST CIRCUIT SEE FIGURE 13
18 24 30
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
ISD , Reverse Drain Current (A)
TJ = 25 C TJ = 150 C
OPERATION IN THIS AREA LIMITED BY RDS(on)
100
10
I D , Drain Current (A)
10
1
1
0.1 0.2
V GS = 0 V
0.8 1.4 2.0 2.6
0.1 1
TC = 25 C TJ = 150 C Single Pulse
10 100 1000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRFE130, JANTX-, JANTXV-, 2N6796U Device
10.0
VDS VGS
RD
8.0
D.U.T.
+
I D , Drain Current (A)
RG
-VDD
6.0
10V
Pulse Width 1 s Duty Factor 0.1 %
4.0
Fig 10a. Switching Time Test Circuit
2.0
VDS 90%
0.0 25 50 75 100 125 150
TC , Case Temperature ( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJC )
10
D = 0.50 1 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 P DM t1 t2
0.1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
IRFE130, JANTX-, JANTXV-, 2N6796U Device
400
EAS , Single Pulse Avalanche Energy (mJ)
TOP BOTTOM
300
15 V
ID 3.3A 5.0A 8.0A
VD S
L
D R IV E R
200
RG
1 20V
D .U .T
IA S tp
+ - VD D
A
0 .0 1
100
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D S S tp
0 25 50 75 100 125 150
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
0 12V
.2F .3F
QG
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
IG
ID
Charge
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
IRFE130, JANTX-, JANTXV-, 2N6796U Device
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
IRFE130, JANTX-, JANTXV-, 2N6796U Device
Notes:
Repetitive Rating; Pulse width limited by @ VDD = 50 V, Starting TJ = 25C,
maximum junction temperature. EAS = [0.5 * L * (IL2) ] Refer to current HEXFET reliability report. Peak IL = 8.0A, VGS =10 V, 25 RG 200 Pulse width 300 s; Duty Cycle 2% K/W = C/W
ISD 8.0A, di/dt 480 A/s,
VDD BVDSS, TJ 150C Suggested RG = 2.35
Case Outline and Dimensions -- Leadless Chip Carrier (LCC) Package
IR Case Style Leadless Chip Carrier (LCC)
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 11/97

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